Buried layers (N-type buried layers (NBL) and P-type buried layers (PBL)) are often used in mixed signal technologies to improve component performance. These buried layers are used for vertical isolation, punchthrough suppression, breakdown improvement, series resistance reduction, and parasitic gain reduction in high-voltage analog devices. These buried layers are also used to generate alignment markers for subsequent post epitaxial (EPI) photo processes.
Unfortunately, as shown in Prior Art FIG. 1, the apparent location of the buried layer (BL) marker can be shifted by several microns during EPI growth on off-axis starting materials. Additionally, thorough analysis indicates that the buried layer shift can significantly impact electrical device behavior. Consequently, precise determination and monitoring of buried layer shift due to EPI growth is critical in technology development and manufacturing. Buried layer shift tolerance not only affects inter-device spacing but also affects device size and can potentially make the device larger. Further, a larger buried layer shift tolerance requires a larger buried layer overlap to account for process variation and guarantee component performance. Tightening the buried layer shift tolerance would help reduce the design rules and then reduce the die size.
Historically, the wafers have been cross-sectioned and scanning electron microscope (SEM) data of the cross-sectioned portion has been used to calculate the offset needed to compensate for this shift. However, this is a very destructive and costly process and the data it provides is very limited. Moreover, and possibly most limiting, the cross-sectioning and SEM analysis, because of its destructive nature, is only performed on a very small percentage of the wafers. For example, the cross-sectioning is often only performed at a single location on a single wafer in a lot of wafers. As one would expect, this provides limited quantities of data. Moreover, this does not allow for wafer-to-wafer analysis or within wafer analysis that is highly beneficial in the manufacture of semiconductor devices.
Accordingly, what is needed in the art is a new process for determining and accounting for the aforementioned buried layer shifts without experiencing the drawback of the prior art methods.